The aim of this academic physical design kit (APDK) is to
introduce circuit designers to the top-down design
methodology of mixed-signal
full-custom integrated circuits (ICs) in CMOS
For this purpose, the following freely
available electronic design automation (EDA)
proposed for both the schematic and the physical IC design
by Peardrop Design Systems is an IC schematic and
mask layout editor, programmable netlister and
physical verification tool featuring Python
language scripting. More information can be found
with integrated optimization
the CACD Group at University of Ljubljana is a
port of the Berkeley SPICE3F5 electrical simulator
featuring Nutmeg language scripting, together with
a custom optimization tool and the Georgia Tech
Research Institute XSpice high-level multi-domain
event-driven engine. The resulting simulation
suite can perform native mixed-signal circuit and
system simulation and optimization. More
information can be found at http://fides.fe.uni-lj.si/spice.
The APDK incorporates all the required technological
information for the simple 2.5um 1P2M PiP CMOS technology
(CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be
easily customized to extend its coverage to complex CMOS
In order to gain hands-on experience, the 100-page APDK
documentation comes with a complete
set of exercises including: the mixed-signal
design at architectural level of a Delta-Sigma modulator
(DSM) for ADC, the functional specification of the DSM
basic building blocks, the automatic circuit optimization
at transistor level of an OpAmp as one of these blocks,
the full-custom analog layout design of the optimized
OpAmp circuit, and the physical verification and
post-layout simulation of the OpAmp layout.
After completing the above training, IC designers should
be able to go from the functional simulation at
architecture level to the tape-out of the corresponding
layout for its CMOS integration at the semiconductor
site is set up!
||Rationalized use of
meter units for Glade extraction.
version of the manual.
of Glade OpenGL graphics...
process/matching device models.
layout generation from schematic.
matching groups at Glade schematic level!
Glade LVS process and reports...
||New Glade schematic
Glade technology and design libraries...
||Glade now supports
design-rule-driven (DRD) layout edition!
||New Gemini LVS