Academic Physical Design Kit
 CNM25 Edition
 

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Introduction

The aim of this academic physical design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies.

For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design stages:

Glade (GDS, LEF and DEF editor) by Peardrop Design Systems is an IC schematic and mask layout editor, programmable netlister and physical verification tool featuring Python language scripting. More information can be found at http://www.peardrop.co.uk/glade.



SpiceOpus (SPICE with integrated optimization utilities) by the CACD Group at University of Ljubljana is a port of the Berkeley SPICE3F5 electrical simulator featuring NUTMEG language scripting, together with a custom optimization tool and the Georgia Tech Research Institute XSpice high-level multi-domain event-driven engine. The resulting simulation suite can perform native mixed-signal circuit and system simulation and optimization. More information can be found at http://fides.fe.uni-lj.si/spice.

The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to complex CMOS technologies.

In order to gain hands-on experience, the 100-page APDK documentation comes with a complete set of exercises including: the mixed-signal design at architectural level of a Delta-Sigma modulator (DSM) for ADC, the functional specification of the DSM basic building blocks, the automatic circuit optimization at transistor level of an OpAmp as one of these blocks, the full-custom analog layout design of the optimized OpAmp circuit, and the physical verification and post-layout simulation of the OpAmp layout.

After completing the above training, IC designers should be able to go from the functional simulation at architecture level to the tape-out of the corresponding layout for its CMOS integration at the semiconductor foundry.


News

2018.04.16: Dynamic net highlight and segment remove in schematic wires.
2018.04.03: General documentation update.
2018.03.15: Mixed schematic and extracted SPICE netlisting.
2018.02.03: New PCells and netlisting options for CNM25TechLib.
2018.01.19: SPICE3Lib now supports design variables!
2018.01.12: APDK new release version 2018_01_12.
2018.01.11: Glade XML configuration file with multiple switch/stop-list profiles.
2017.12.04: Bus notation for wires and instances...
2017.11.12: Yank+Paste between cellviews. Monochrome SVG output for schematics documentation. Bindkeys stored in local configuration file.
2017.11.01: APDK new release version 2017_11_01.
2017.10.31: New XtendedLib with XSpice code models for transient-noise and file-driven analog sources.
2017.10.30: Multi-layer DRD and improved matching group editor. Updated CNM25 techfile to include the new DRD rules.
2017.10.28: Migration to Glade library format version 520 for better EDIF import/export compatibility.
2017.06.09: Poster presented at IEEE ISCAS 2017 in Baltimore, MD, USA
2017.05.14: Web site is set up!
2017.05.12: Rationalized use of meter units for extraction.
2017.05.09: APDK new release version 2017_05_10.
2017.05.08: First complete version of the manual.
2017.05.07: Overall reworking of OpenGL graphics...
2017.04.30: Unified process/matching device models.
2017.04.21: Improved layout generation from schematic.