Academic Physical Design Kit
 CNM25 Edition
 

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Introduction

The aim of this academic physical design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies.

For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design stages:

Glade (GDS, LEF and DEF editor) by Peardrop Design Systems is an IC schematic and mask layout editor, programmable netlister and physical verification tool featuring Python language scripting. More information can be found at http://www.peardrop.co.uk/glade.



SpiceOpus (SPICE with integrated optimization utilities) by the CACD Group at University of Ljubljana is a port of the Berkeley SPICE3F5 electrical simulator featuring Nutmeg language scripting, together with a custom optimization tool and the Georgia Tech Research Institute XSpice high-level multi-domain event-driven engine. The resulting simulation suite can perform native mixed-signal circuit and system simulation and optimization. More information can be found at http://fides.fe.uni-lj.si/spice.

The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to complex CMOS technologies.

In order to gain hands-on experience, the 100-page APDK documentation comes with a complete set of exercises including: the mixed-signal design at architectural level of a Delta-Sigma modulator (DSM) for ADC, the functional specification of the DSM basic building blocks, the automatic circuit optimization at transistor level of an OpAmp as one of these blocks, the full-custom analog layout design of the optimized OpAmp circuit, and the physical verification and post-layout simulation of the OpAmp layout.

After completing the above training, IC designers should be able to go from the functional simulation at architecture level to the tape-out of the corresponding layout for its CMOS integration at the semiconductor foundry.


News

2017.05.14: Web site is set up!
2017.05.12: Rationalized use of meter units for Glade extraction.
2017.05.09: First complete version of the manual.
2017.05.07: Overall reworking of Glade OpenGL graphics...
2017.04.30: Unified process/matching device models.
2017.04.21: Improved Glade layout generation from schematic.
2017.04.07: Management of matching groups at Glade schematic level!
2017.03:24: Enhancement of Glade LVS process and reports...
2017.03.13: New Glade schematic check menu.
2017.03.06: Splitting between Glade technology and design libraries...
2017.02.05: Glade now supports design-rule-driven (DRD) layout edition!
2017.01.27: New Gemini LVS options available...