Introduction The aim of this academic process design kit (APDK) is to introduce circuit designers to the top-down design methodology of mixed-signal full-custom integrated circuits (ICs) in CMOS technologies. For this purpose, the following freely available electronic design automation (EDA) tools are proposed for both the schematic and the physical IC design stages: Glade (GDS, LEF and DEF editor) by Peardrop Design Systems is an IC schematic and mask layout editor, programmable netlister and physical verification tool featuring Python language scripting. More information can be found at www.peardrop.co.uk. SpiceOpus (SPICE with integrated optimization utilities) by the CACD Group at University of Ljubljana is a port of the Berkeley SPICE3F5 electrical simulator featuring NUTMEG language scripting, together with a custom optimization tool and the Georgia Tech Research Institute XSpice high-level multi-domain event-driven engine. The resulting simulation suite can perform native mixed-signal circuit and system simulation and optimization. More information can be found at fides.fe.uni-lj.si/spice. The APDK incorporates all the required technological information for the simple 2.5um 1P2M PiP CMOS technology (CNM25) from IMB-CNM(CSIC). Anyway, this APDK can be easily customized to extend its coverage to more complex CMOS technologies. In order to gain hands-on experience, the 100-page APDK documentation comes with a complete set of exercises including: the mixed-signal design at architectural level of a Delta-Sigma modulator (DSM) for ADC, the functional specification of the DSM basic building blocks, the automatic circuit optimization at transistor level of an OpAmp as one of these blocks, the full-custom analog layout design of the optimized OpAmp circuit, and the physical verification and post-layout simulation of the OpAmp layout. After completing the above training, IC designers should be able to go from the functional simulation at architecture level to the tape-out of the corresponding layout for its CMOS integration at the semiconductor foundry. News 2024.04.09: APDK release version 2024_04_09 + Update to Glade 6.x series (Qt6) 2023.03.29: APDK release version 2023_03_29 + Update to Glade 5.0.59 + Minor corrections in documentation 2022.03.08: APDK release version 2022_03_08 + Bug fixing of Python3 pCells + Bug fixing of multi-part paths (MPPs) + General documentation update 2021.04.01: APDK release version 2021_04_01 + Migration to Glade 5.x series (Qt5 and Python 3) + SpiceOpus plot to PDF + General documentation update 2020.04.19: APDK release version 2020_04_19 + Update to Glade 4.7.37 and SpiceOpus 2.33 + Migration to Glade library format version 600 2018.12.15: APDK release version 2018_12_15 + Glade manual incorporated into documentation + Aesthetic corrections in several XSpice symbols + SpiceOpus log file is automatically generated + Glade dynamic net highlight in schematic wires + General documentation update + Glade mixed schematic and extracted SPICE netlisting + New PCells and netlisting options for CNM25TechLib + SPICE3Lib now supports design variables! 2018.01.12: APDK release version 2018_01_12 + Glade XML config. file with multiple switch/stop-list profiles + Glade bus notation for wires and instances + Glade Yank & Paste between cellviews + Glade monochrome SVG output for schematics + Glade bindkeys stored in local configuration file 2017.11.01: APDK release version 2017_11_01 + Custom XtendedLib (XSpice transient noise and file sources) + Glade improved matching group editor + CNM25 techfile with multi-layer DRD rules + Migration to Glade library format version 520 2017.06.09: Poster at IEEE ISCAS 2017 in Baltimore, MD, USA. 2017.05.14: Web site is set up!