Standard material: 100 mm diameter Silicon substrates

*CNM25 is a 2.5 µm CMOS mixed analog/digital process with two metal layers and two polysilicon layers to form poly/poly capacitors. A Cadence Design Tool kit is available for CNM25 and CNMBiCMOS25 (an expansion of CMOS25 with bipolar output stages). The design kit covers from HDL level entry to physical design (Verilog and VHDL synthesis, schematic entry, Verilog digital simulation, DRC, LVS, extraction and SPICE simulation, P&R...) and includes standard cell library and an I/O library.
 

** 125, 150 mm wafer rerouting capabilities